학력
Ph.D. in Electrical Engineering, 2009
KAIST, Daejeon, Republic of Korea
B.S. in Electrical Engineering and Computer Science, 2004 (Summa Cum Laude)
KAIST, Daejeon, Republic of Korea
주요 경력
Associate Professor, Feb. 2016 - Present
Dept. of Electrical Engineering and Information Technology, Seoul National University of Science and Technology (SeoulTech)
Associate Professor, Mar. 2010 - Feb. 2016
Dept. of Electronics Engineering, Chungnam National University
Senior Engineer, July 2009 - Feb. 2010
Samsung Electronics, Republic of Korea
Cellular Modem SoC Design
Research Assistant, Mar. 2004 - June. 2009
Integrated Computer Systems Lab. (Supervisor : Prof. In-Cheol Park)
Research on CPU core / SoC Design for Various Systems
Summer Intern, June 2002 - July 2002
Samsung Electronics, Republic of Korea
Digital Communication System Simulator Design
연구 분야
SoC (System-on-Chip) Design
CPU / DSP Design
VLSI for Signal Processing Systems
Hardware Security
Biomedical System
주요논문 및 저서
1. I. Choi and J. -H. Kim, "Area-optimized multi-standard AES-CCM security engine for IEEE 802.15.4/802.15.6," IEIE JSTS, to appear
2. H. Ko, T. Lee, J. -H. Kim, J. Park, and J. P. Kim, "Ultra Low Power Bioimpedance IC with Intermediate Frequency Shifting Chopper," IEEE TCAS-II, to appear
3. J. P. Kim, J. -H. Kim, and H. Ko, "Low Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Inteference Compensation," MDPI Sensors, Dec. 2015
4. H. Kim, Y. Lee, and J. -H. Kim, "Low-Complexity CRC-Aided Early Stopping Unit for Parallel Turbo Decoder," IET EL, Oct. 2015
5. H. Kim, W. Byun, I .Choi, J. -Y. Lee, and J. -H. Kim, "Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced," IEEE TCAS-II, Sep. 2015
6. Y. Ku, W. Byun, J. -H. Kim, and H. C. Kim, "Noise-Robust Auditory Evoked Potential Extraction Algorithm," IEEE EMBC 2015
7. J. -H. Kim, J. -Y. Lee, and A. Ki, "Core-A: 32-bit Synthesizable Processor Core," IEIE SPC, Apr. 2015
8. W. Byun, H. Kim, and J. -H. Kim, "High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement," IEIE JSTS, Aug. 2014
9. H. -J. Kang, J. -Y. Lee, and J. -H. Kim, "Low-Complexity Twiddle Factor Generation for FFT Processor," IET EL, Dec. 2013
10. J. -H. Kim and I. C. Park, "A Unified Parallel Radix-4 Turbo Decoder for Mobile WiMAX and 3GPP-LTE," IEEE CICC 2009
11. J. -H. Kim and I. C. Park, "Bit-level Extrinsic Information Exchange Method for Double-Binary Turbo Codes," IEEE TCAS-II, Jan. 2009
12. J. -H. Kim and I. C. Park, "A 50Mbps Double-Binary Turbo Decoder for WiMAX Based on Bit-level Extrinsic Information Exchange," IEEE A-SSCC 2008
13. J. -H. Kim and I. C. Park, "Double-Binary Circular Turbo Decoding Based on Border Metric Encoding," IEEE TCAS-II, Jan. 2008
저널 논문
◾ Fast auditory evoked potential extraction with real-time singular spectrum analysis, ELECTRONICS LETTERS, vol.53 No.16 pp.1094~1095, 2017김지훈
◾ Low Noise CMOS Temperature Sensor with On-Chip Digital Calibration, SENSORS AND MATERIALS, vol.29 No.7 pp.1025~1030, 2017김지훈
◾ High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol.64 No.7 pp.1937~1948, 2017김지훈
◾ Low power wireless SoC platform for wearable IoT applications, Advanced Science Letters, vol.22 No.11 , 2016김지훈
◾ 2048-point fast Fourier transform processing based on twiddle factor reduction and dynamic data scaling, Advanced Science Letters, vol.22 No.11 pp.3662~3666, 2016김지훈
◾ A digital hearing aid SoC based on AHB-lite bus matrix, Advanced Science Letters, vol.22 No.11 , 2016김지훈
◾ A 2-stage low noise amplifier in 90 nm CMOS for 2.4 GHz applications, Advanced Science Letters, vol.22 No.11 pp.3228~3231, 2016김지훈
◾ 보안을 위한 프로세서 기술 동향, 전자공학회지, vol.43 No.7 pp.68~72, 2016김지훈
◾ Area-Optimized Multi-Standard AES-CCM Security Engine for IEEE 802.15.4/802.15.6, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol.16 No.3 pp.293~299, 2016김지훈
◾ 1.4 Gbps 비이진 LDPC 코드 복호기를 위한Fully-Parallel 아키텍처, 전자공학회논문지, vol.53 No.4 pp.48~58, 2016김지훈
◾ Ultralow-Power Bioimpedance IC With Intermediate Frequency Shifting Chopper, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol.63 No.3 pp.259~263, 2016김지훈
학술대회
◾ 김도균, 손장재, 구윤서, 김지훈, SSVEP/P300 기반 BCI 시스템을 위한 Speller설계 고려사항 분석, 2016년 대한전자공학회 추계학술대회 논문집, 대구 EXCO, 2016김지훈
◾ Wooseok Byun, Yunseo Ku, Ji-Hoon Kim, Low Power Sensor Interface SoC using PCA-Based Hardware Accelerator, CANADA-KOREA CONFERENCE ON SCIENCE AND TECHNOLOGY 2016, Westin Hotel, Ottawa, 2016김지훈
◾ Injun Choi, Ji-Hoon Kim, Two Step Forward Backward Architecture for Non-Binary LDPC Decoder, 제23회 한국반도체학술대회, 강원도 하이원리조트, 2016김지훈
◾ Hoo-Sung Lee, Ik-Jae Chun, Moon-Sik Lee, Ji-Hoon Kim, A Simple and Fast Giga Link between a Host and a FPGA, 제23회 한국반도체학술대회, 강원도 하이원리조트, 2016김지훈
◾ Wooseok Byun, Ji-Hoon Kim, Real-Time Hardware Implementation of Noise-Robust Auditory Evoked Potential Extraction Algorithm, 제23회 한국반도체학술대회, 강원도 하이원리조트, 2016김지훈
연구프로젝트
◾ 캡슐내시경을 위한 디지털신호처리 및 베이스밴드 모뎀 연구, (주)인트로메딕, 2017.09.~2019.09.김지훈
◾ 해킹 불가능한 보안 SoC 개발, 삼성전자(주), 2016.06.~2019.05.김지훈
◾ 마비 환자의 의사소통을 위해 시각유발전위를 활용한 헤드셋 형 고속/저전력 뇌-컴퓨터 인터페이스 시스템 개발, 한국연구재단, 2016.05.~2018.04.김지훈
◾ 연속근사형 아날로그 디지털 변환 회로용 디지털 IP개발, (주)실리콘하모니, 2016.03.~2016.06.김지훈
◾ 다표준 무선 통신 기반의 고성능 뇌-컴퓨터 인터페이스 SoC 설계, 한국연구재단, 2015.11.~2018.10.김지훈
◾ 저전력 모뎀 SoC 플랫폼 및 응용 시스템 개발, 한국연구재단, 2015.09.~2016.06.김지훈
기타(학회활동 등)
A. 주요활동
Steering Committee, IDEC (IC Design Education Center), KAIST
IEEE CAS Seoul Chapter
IEEE SSCS Seoul Chapter
ACM SIGARCH Korea Chapter
ACM SIGDA Korea Chapter
B. 수상 실적
Best Poster Award (Division of System LSI), Korean Conference on Semiconductor (2015)
Special Award, Korea Semiconductor Design Contest (2008)
1st Place Award, International SoC Design Conference (ISOCC) Chip Design Contest (2008)
Best Design Award, Dongbu HiTek IP Design Contest (2007)
Young-Han Kim Global Leader Scholarship (2004)
Min-Hwa Lee Scholarship (2002)
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